4 megabit 5 volt cmos flash eeprom dpz128x32xp/xhp description: the dpz128x32xp/xhp is a 4 megabit 5 volt only cmos flash eeprom (electrically in-system programmable and erasable rom memory) module. the module is built with four 128k x 8 flash memory devices. the dpz128x32xp/xhp can be user configurable as 512k x 8, 256k x 16 or 128k x 32 bits. the dpz128x32xp/xhp is ideal for use in systems that require in-system periodic code updates, or for use as a high speed nonvolatile storage medium. features: user definable configuration: 512k x 8, 256k x 16 or 128k x 32 fast read access times: 70, 90, 120, 150ns low power: 120ma maximum active (32 bit mode) 400 m a maximum standby (cmos) 10,000 erase/program cycles minimum 5 volt only in-system programming ttl-compatible inputs and outputs packages available: 68- ?j? leaded plastic surface mount module 68- gull - leaded plastic surface mount module 512kx8/256kx16/128kx32, 150 - 250ns, pga 30a169-00 a this document contains information on a product that is currently released to production at dense-pac microsystems, inc. dense-pac reserves the right to change products or specifications herein without prior notice. pin-out diagram functional block diagram pin names a0 - a16 address inputs i/o0 - i/o31 data input/output ce 0 - ce 3 low chip enables we write enable oe output enable v dd power (+5v) v ss ground n.c. no connect 30a169-00 rev. a 1
dpz128x32xp/xhp dense-pac microsystems, inc. device operation data bus width: the dpz128x32xp/xhp is configured with separate ce ?s and data i/o?s to allow the module to be used in an 8 bit, 16 bit or 32 bit environment. when either the software data protect or the chip erase feature is used, the specific data shown in the algorithms must be written to each device that the operation is being perfomed on. an example would be if the module is used in a 32 bit system, the data called out in the third data load for the software data protect alogrithm is a0h. the data of a0a0a0a0h should be written to the dpz128x32xp/xhp. read: the dpz128x32xp/xhp is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual line control gives designers flexibility in preventing bus contention. byte load: a byte is loaded into the device by applying a low pulse to we or ce with ce or we low (respectively) and oe high. on the falling edge of ce or we , whichever occurs last, the address is latched. on the rising edge of ce or we , whichever occurs first, the data is latched. this operation is used to load data into the 128 byte page for programming or to load software codes for data protection or 5 volt chip erase. program: this dpz128x32xp/xhp is programmed in a page mode only. a7 to a16 are used to specify the page address and they must be valid during each high to low transition of we or ce . a0 to a6 are used to specify the address of the byte within the 128 byte page. the data can be loaded into the page in any order. all of the bytes within the page must be written, otherwise any unwritten bytes will be erased to read ffh. the locations to be reprogrammed need not be erased prior to programming as with other flash technologies. each new byte to be loaded must have its high to low transition of we or ce within 150 m s of the preceding bytes high to low transition. if a high to low transition is not detected within 150 m s of the last high to low transition, the internal programming period will begin. data polling: the dpz128x32xp/xhp features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on the msb (most significant bit, i/o7,i/o15,i/o23 and i/o31) of the device or devices being programmed at that time. when the programming cycle is complete, the data will be true on all outputs and the next programming cycle can begin. data polling can begin at any time during the programming period. toggle bit: the dpz128x32xp/xhp has an additional method for determining if the program period or erase cycle is completed. during a program or erase operation, successive attempts to read data from the device will result in i/o6, i/o14, i/o22 or i/o30 (depending on the device or devices the operation is being performed on) toggling between one and zero. once the program or erase period has completed, the i/o pin will stop toggling and valid data can be read. examining the toggle bit can begin at any time during the program or erase period. hardware data protection: the devices used on the dpz128x32xp/xhp incorporate several hardware features for data protection. if v dd falls below 3.8v (typ.), the program function is inhibited. during power up, programming will be inhibited 5ms (typ.) after v dd has reached the v dd sense level. another hardware feature is a noise filter on ce or we . any pulse less than 15ns (typ.) will not initiate a program cycle. finally, programming is inhibited by holding any one of: oe low, ce high or we high. software data protection: the dpz128x32xp/xhp features software data protection that can be enabled and disabled by the end user. the software protection is enabled by writing a series of three commands to specific addresses with specific data using the page program timing specifications. once the software protection is enabled, the same three commands must precede a program cycle. the software protection will remain active until the disable command algorithm is issued. power transitions will not reset the software protection. the data will be protected against inadvertent programming during power transitions. the dpz128x23vt/vtp is shipped with the software data protection disabled. 5 volt chip erase: each device on the dpz128x32xp/xhp can be erased at one time by using a six byte software code. the erase code consists of six byte load commands to specific address locations with specific data patterns. after the command is entered, every location in the device being erased will be set to a high state (ffh). 30a169-00 rev. a 2
dense-pac microsystems, inc. dpz128x32xp/xhp recommended operating range 1 symbol characteristic min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v v ih input high voltage 2.0 v v il input low voltage 0.8 v absolute maximum rating 3 symbol parameter value unit t stc storage temperature -65 to + 150 c t bias temperature under bias -55 to +125 c v dd supply voltage 1 -0.6 to + 6.25 v v i/o input/output voltage 1 -0.6 to v dd +0.6 v v oe oe input voltage 1 -0.6 to +13.5 v ac test conditions input pulse level 0v to 3.0v input pulse rise and fall times 5ns* input and output timing reference levels 1.5 v * transition between 0.8 and 2.2v. output load float c l parameters measured 1 100pf except t df 2 5pf t df truth table mode ce oe we i/o pin standby h x x high-z read l l h d out write l h l d in write inhibit x l x high-z write inhibit x x h high-z 5.0v chip erase l h l - output disable x h x high-z l = low h = high x = don?t care capacitance 4 : t a = 25c, f = 1.0mhz symbol parameter max. unit condition c ce chip enable 15 pf v in = 0v c adr address input 35 c we write enable 35 c oe output enable 35 c i/o data input/output 20 figure 1: output load ** including probe and jig capacitance. dc operating characteristics: over the operating ranges. symbol characteristics test conditions x 32 x 16 x8 unit min. max. min. max. min. max. i cc operating supply current ce = oe = v il all i/o = 0ma f = 5mhz 200 105 60 ma i sb1 v dd current standby (ttl) ce = v ih 12 12 12 ma i sb2 v dd current standby (cmos) ce = v dd -0.3vdc 1.2 1.2 1.2 ma i il input leakage current v in - v dd max. -40 +40 -40 +40 -40 +40 m a i ol output leakage current v out - v dd max. -10 +10 -20 +20 -40 +40 m a v il input voltage low 0.8 0.8 0.8 v v ih input voltage high 2.0 2.0 2.0 v v ol output voltage low i out = 2.1ma 0.45 0.45 0.45 v v oh output voltage high i out = -400 m a 2.4 2.4 2.4 v +5v 1.8k w 1.3k w d out c l ** 30a169-00 rev. a 3
dpz128x32xp/xhp dense-pac microsystems, inc. a.c. operating conditions and characteristics - read cycle: over operating ranges no. symbol parameter 70ns 90ns 120ns 150ns unit min. max. min. max. mn. max. min. max. 1 t acc address to output valid 70 90 120 150 ns 2 t ce chip enable to output valid 70 90 120 150 ns 3 t oe output enable to output valid 0 35 0 40 0 50 0 70 ns 4 t df chip enable or output enable to float 4 0 25 0 25 0 30 0 40 ns 5 t oh output hold from chip enable, output enable, or address, whichever occurs first 0 0 0 0 ns a.c. byte load characteristics no. symbol parameter min. max. unit 6 t as address setup time 0 ns 7 t oes output enable setup time 0 ns 8 t ah address hold time 50 ns 9 t cs chip select setup time 0 ns 10 t ch chip select hold time 0 ns 11 t wp write pulse width (write enable or chip enable) 90 ns 12 t ds data setup time 35 ns 13 t dh data hold time 0 ns 14 t oeh output enable hold time 0 ns 15 t wph write page width high 100 ns read cycle address ce oe data i/o notes: 1. all voltages are with respect to v ss . 2. -1.0v min. for pulse width less than 20ns (v il min. = -0.3v at dc level). 3. stresses greater than those under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 4. this parameter is guaranteed and not 100% tested. 5. a7 through a16 specify the page address during each high to low transition of we (or ce ) after the software code has been entered. 6. oe must be high when we and ce are both low. 7. all bytes that are not loaded within the page being programmed will be erased to ff. 8. toggling either oe or ce or both oe and ce will operate toggle bit. 9. beginning and ending state of i/o6 will vary. 10. any address location may be used but the address should not vary. 30a169-00 rev. a 4
dense-pac microsystems, inc. dpz128x32xp/xhp a.c. byte load waveforms: we controlled. oe address ce we data in a.c. byte load waveforms: ce controlled. oe address we ce data in waveform key data valid transition from transition from data undefined high to low low to high or don?t care 30a169-00 rev. a 5
dpz128x32xp/xhp dense-pac microsystems, inc. program cycle characteristics no. symbol parameter min. max. unit 16 t wc write cycle time 10 ms 17 t as address setup time 0 ns 18 t ah address hold time 50 ns 19 t ds data setup time 35 ns 20 t dh data hold time 0 ns 21 t wp write pulse width 90 ns 22 t blc byte load cycle time 150 m s 23 t wph write pulse width time 100 ns program cycle waveforms 5, 6, 7 oe ce we a0 - a6 a7 - a16 data software data protect enable algorithm step mode address (a0 - a14) data (i/o0 - i/o7) comment 1 write 5555 hex aa hex dummy write. 2 write 2aaa hex 55 hex dummy write. 3 write 5555hex a0 hex writes enabled data protect state will be activated at end of program cycle. 4 write address data 128 bytes of data are entered. enter data protect stated. 30a169-00 rev. a 6
dense-pac microsystems, inc. dpz128x32xp/xhp software data protect disable algorithm step mode address (a0 - a14) data (i/o0 - i/o7) comment 1 write 5555 hex aa hex dummy write. 2 write 2aaa hex 55 hex dummy write. 3 write 5555 hex 80 hex dummy write. 4 write 5555 hex aa hex dummy write. 5 write 2aaa hex 55 hex dummy write. 6 write 5555hex 20 hex exit data protect state. data protect state will be deactivated at end of program period. 7 write address data 128 bytes of data are entered. chip erase cycle characteristics no. symbol parameter min. max. unit 24 t wc write cycle time 20 ms 25 t as address setup time 0 ns 26 t ah address hold time 50 ns 27 t ds data setup time 35 ns 28 t dh data hold time 0 ns 29 t wp write pulse width 90 ns 30 t blc byte load cycle time 150 m s 31 t wph write pulse width high 100 ns software protect program cycle waveforms 5, 6, 7 oe ce we a0 - a6 a7 - a16 data 30a169-00 rev. a 7
dpz128x32xp/xhp dense-pac microsystems, inc. software chip erase algorithm step mode address (a0 - a14) data (i/o0 - i/o7) comment 1 write 5555 hex aa hex dummy write. 2 write 2aaa hex 55 hex dummy write. 3 write 5555 hex 80 hex dummy write. 4 write 5555 hex aa hex dummy write. 5 write 2aaa hex 55 hex dummy write. 6 write 5555hex 10 hex data polling may be used to determine the end of the erase cycle by checking any address for data equal to ff. after loading the six byte code, no byte loads are allowed until the completion of the erase cycle. the erase cycle will time itself to completion within t wc . data polling characteristics 4 no. symbol parameter min. max. unit 32 t dh data hold time 10 ns 33 t oeh output enable hold time 10 ns 34 t oe output enable to output delay * ns 35 t wr write recovery time 0 ns * see t oe spec in ac read characteristic. chip erase cycle waveforms 6 oe ce we a0 - a6 a7 - a16 data 30a169-00 rev. a 8
dense-pac microsystems, inc. dpz128x32xp/xhp toggle bit characteristics 4 no. symbol parameter min. max. unit 36 t dh data hold time 10 ns 37 t oeh output enable hold time 10 ns 38 t oe output enable to output delay* ns 39 t oehp output enable high pulse 150 ns 40 t wr write recovery time 0 ns * see t oe spec in ac read characteristic. data polling waveforms 6 we ce oe i/o7, i/o15, i/o23, o/o31 a0 - a16 toggle bit waveforms 8, 9, 10 we ce oe i/o6, i/o14, i/o22, i/o30 30a169-00 rev. a 9
dpz128x32xp/xhp dense-pac microsystems, inc. ?j? leaded mechanical drawing ordering information dense-pac microsystems, inc. 7321 lincoln way ? garden grove , california 92841-1431 (714) 898-0007 (800) 642-4477 (outside ca) ? fax: (714) 897-1772 ? http://www.dense-pac.com gull-leaded mechanical drawing 30a169-00 rev. a 10
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